1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a programming pulse generation circuit and a non-volatile memory apparatus having the same.
2. Related Art
Examples of the nonvolatile memory apparatus include a flash memory apparatus, a phase-change memory apparatus, a magnetic memory apparatus, and the like. Among the memory apparatuses, the phase-change memory apparatus and the magnetic memory apparatus are nonvolatile memory apparatuses that are able to write and sense data according to a current driving method.
The level of data stored in each memory cell forming the phase change memory apparatus is determined according to a crystalline state of a phase change material. When data is written into a phase change memory cell, the phase change material becomes molten due to a write current from a bottom electrode to a top electrode that passes through it. The resistance based on the cooling rate of the phase change material dictates the reset and set states. A high-resistance state defines a reset state, and a low-resistance statedefines a set state.
FIG. 1 is a graph showing resistance distributions of phase change memory cells.
FIG. 1 illustrates a resistance distribution RRST when phase change materials forming the phase change memory cells are in a high-resistance state, i.e., a reset state, and a resistance distribution RSET when the phase change materials are in a low-resistance state, i.e., a set state.
Referring to FIG. 1, since the data distributions in the set state and the reset state are wide, a sensing margin is reduced, which may lead to an error during a data read operation. There is a demand for a method to solve this problem.
In order to prevent a data read failure, a high-sensitivity sense amplifier may be adopted. However, this may need to be done cautiously since the high-sensitivity sense amplifier occupies a large area, thereby creating an obstacle to miniaturization efforts of the semiconductor apparatus.
Thus, a method of concentrating a resistance distribution of memory cells through a program and verify (PNV) operation for the memory cells may alternatively be used.
FIG. 2 is a graph explaining resistance distributions of memory cells after a PNV operation.
As the PNV operations are repetitively performed, the data distribution is more concentrated, sufficiently increasing the sensing margin. The repetition number of PNV operations is an important factor to determine a program operation time. As the PNV repetition number increases, the program operation time increases.
FIG. 3 is a configuration diagram of a conventional program pulse generation circuit. In particular, FIG. 3 illustrates a circuit to generate a pulse for programming set data.
In general, a slow quenching pulse is provided to place a phase change memory cell into a set state. The circuit illustrated in FIG. 3 generates a slow quenching pulse.
Referring to FIG. 3, the program pulse generation circuit 10 may include a driving signal generator 12 and a set pulse generator 14.
The driving signal generator 12 is configured to generate a driving signal CSB in response to an enable signal EN. The set pulse generator 14 includes a plurality of switching elements configured to drive a current, according to a driving signal CSB and a plurality of transmission gates configured to be switched by set pulse control signals SETP<1:15> and its complement signals /SETP<1:15>, to an output node IOUT. Here, each of the switching elements is designed to drive the same amount of current X(1/N).
The set pulse generator 14 illustrated in FIG. 3 includes 15 transmission gates switched by the set pulse control signals SETP<1:15>. As the set pulse control signals SETP<1:15> are sequentially disabled, a slow quenching set pulse is applied to the output node IOUT.
FIG. 4 is a diagram showing an output pulse of the program pulse generation circuit illustrated in FIG. 3.
When the set pulse control signals SETP<1:15> are all enabled, the output node IOUT provides a melting current IMelting capable of melting a phase change material. The set pulse control signals SETP<1:15> are then sequentially disabled to slowly cool down the phase change material. Typically, this is done by disabling the set pulse control signal associated with the transmission gate farthest away from the output node IOUT.
As the set pulse control signals SETP<1:15> are sequentially disabled after the melting current IMelting is applied to the output node IOUT for a designated time, the current applied to the output node IOUT decreases in a stepwise manner as illustrated in FIG. 4. Since the switching elements driven by the driving signal CSB have the same current drivability, the step pulses have the same current reduction X.
FIG. 5 is a diagram showing a form of the program pulse illustrated in FIG. 4 applied to a cell array.
Specifically, the step-type program pulse illustrated in FIG. 4 is applied in such a manner as illustrated in FIG. 5 by driving through a global bit line and a local bit line when the program pulse is applied to the cell array.
However, the step-type program pulse rapidly decreases in the final period thereof. Since the current supply is completely cut off when the final transmission gate is turned off, the final step wave does not gradually decrease, but is rather rapidly cut off.
In many cases, Germanium-Antimony-Tellurium, or GST, is used as a phase change material to form a phase change memory cell. GST is an important factor when the reduction of the final step wave of the program pulse affects cell distribution. As the reduction of the final step wave increases, cell distribution is degraded.
Thus, if the reduction of the final step wave is controlled during the generation of the set pulse, the resistance distribution of phase change memory cells may be improved.